1. Technical Field
The present invention relates to an apparatus for synthesizing signals in general, and in particular to a phase-locked loop circuit. Still more particularly, the present invention relates to a phase-locked loop circuit with dynamic backup.
2. Description of the Prior Art
Phase-locked loop ("PLL") circuits are electronic circuits utilized for locking an output signal in phase and frequency with a reference signal. Traditionally, PLL circuits are found in a variety of data communication devices and telecommunication devices for generating a clock signal synchronous to an external clock signal. In recent years, PLL circuits have often been employed in data processing systems and microprocessors for the purpose of generating a local clock signal that is phase-aligned with a reference clock signal generated by a crystal or another PLL circuit. A common reason for utilizing a PLL circuit within a data processing system is that a PLL circuit is able to synthesize a very stable local clock signal having a clock frequency that is typically higher than the reference clock signal.
A conventional PLL circuit includes a phase comparator (or phase detector), a low-pass filter, and a voltage-controlled oscillator (VCO). In general, the phase comparator compares an input reference signal and an output signal from the VCO in order to generate an error signal that is representative of the phase difference between the reference signal and the VCO output signal. In turn, the error signal is filtered and applied to a control input of the VCO for producing the output signal that tracks the phase and frequency of the reference signal.
Typically, both the low-pass filter and the VCO of a PLL circuit employ analog components, and because of these analog components, PLL circuits are notoriously sensitive to environmental influences. In addition, there are also other sources that affect the performance of a PLL circuit, for example, a noisy or missing input reference signal, a noisy or missing output signal, a noisy or insufficient power supply to the PLL circuits, or extraneous noise picked up by the PLL circuit. Quite often, any one or more of the above factors may lead the PLL circuit output signal to lose lock with the input reference signal. For data transmission systems or data processing systems that demand a certain level of reliability, it is desirable that the output signal clock still be available even when the PLL circuit is losing lock. For this reason, it would be desirable to provide a PLL circuit with dynamic backup such that an associated data transmission system or data processing system may still function properly in the event that the PLL circuit loses lock.